basic logic gates lab report discussion

G^@r#Rd+jJFx :{n6nR!c:@M3vCc$@K:5c0vA#oQLf7WW7(;bDd|7. T=N$TR1$!/zS?k1lRD,^v \z/bu11JN8or0Fsm:v"&71lRZHf'8& 5C\! WebDeMorgans Equivalent Gates The standard logic gates i.e. An inverter can be made from a NAND gate by connecting all of the inputs together and creating, a single input as shown below. Include Boolean algebra, truth tables, and logic diagrams for the circuit reconstructed with only NOR gates. This preview shows page 1 - 3 out of 7 pages. 0000004222 00000 n %%EOF The simulation will test the 8 possible combinations for x, y and c_in. BHG&-xkb63->tL6m,e-\N7/PC}-X6u\HR'M,1``qw4ovA[r c7 q#\Dp6`u]vq*feow[o-CtC[A U%;7w~CHWw>w;qY()\7Eq0+B!^ ZXu^8Q?~|'p&?r%gL(ox`:/YKKs_(!Ha)k 299 0 obj<>stream t(%@ What do you observe? endstream endobj startxref 0000004295 00000 n Output (LED) 0 1 1 1. Measure the propagation delay for the circuit and compare it to that of the NAND gate. Familiarization with the breadboard 2. Now connect, in parallel, the remaining 5 inverters to the output of the inverter, and measure the propagation delay of the first inverter again. A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family. Connect one of the inverters as shown in Fig. A gate can be extended to have multiple inputs if the binary operation it represents is commutative and associative. ECE 394 Lab 1: Logic Gates and Logic Families - New Jersey I.e. 0000012195 00000 n 2-input AND gate b. WebPart 2: Proteus (Simulation Software) Proteus has many features to generate both analog and digital results over a virtual environment. Implement the basic logic gates using universal gates Please see the online tutorial for instructions on how to use this software. if VDD = 5V, its noise margin is 2V). WebA logic gate is an elementary building block of a digital circuit. Nguyen Quoc Trung. WebThere are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. Now we will look at the operation of each. To They are widely used in large scale integrated circuits because of their high component density and relatively low power consumption. 2). After this creation was completely done and tested to, make sure it ran properly. Procedure : 1. 0000007396 00000 n Webnot sufficient to implement complex digital logic functions. 3) Reconstruct the circuit above using only NAND gates. Web7400 (NAND gate) 7402 (NOR gate) Discussion: NAND and NOR gates are two important gates because they are considered universal gates. gate type. 0000002673 00000 n Toun derstand some of the later instructions in the lab, complete the analysis required by Discussion Topic #3 before continuing. GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. The three AND gates that I mentioned above would have the inputs of, each input from the three. We will be using a full adder which is a logic circuit which has three one-bit inputs (X, Y, and Cin) and, Cout), where X and Y are the bits to be added. Electrical and Computer Engineering Department, The objective for this lab will be us designing and verifying a full adder which will be used to create the, 4-bit adder. universal gate is a gate which can implement any Boolean function without need to use any other WebThe most efficient way to quickly reach the fault location is to exploit the low logic level dominance in AND gate and high logic level dominance in OR gate. f?3-]T2j),l0/%b

WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. 0000001112 00000 n ?pn\}(n~~jA;8@'gNpB[hq\^(E=o}^ {*. 0000001929 00000 n Being able to understand the basic of, Logic statements as well as follow given instruction remain the key to complete the lab, The Logic Gate Lab tests the students logic statement and the ability to follow given, The students will watch an instructional video that provides an example on how to use, the tinkercad website to complete the lab. Draw the circuit for the expression of XNOR Gate using basic gates. 0000004299 00000 n Propagation delay is the time delay for a signal transition to propagate from input to output when the binary input signals change in value. A logic gate may have one or more inputs, but it has only one output. The relationship between the possible values of input and output voltage is expressed in the form of a table called truth table or table of combinations. Truth table of a Logic Gates is a table that shows all the input and output possibilities for the logic gate. 7. 0000006629 00000 n logical Boolean expression if appropriately designed. Learn more about accessibility on the OpenLab, New York City College of Technology | City University of New York, EMT Laboratories Open Education Resources, Lab 0: Digital Trainer and Troubleshooting, Lab 01: Schematic Diagrams and Electronic Testing Equipment, Lab 05: Universal Capability of NAND and NOR Gates, Lab 11: Introduction to D and J-K Flip-Flop. Due to the fact that CMOS logic is more widely used in VLSI digital circuits than any other logic, students are required to understand the basic structure of the CMOS logic. A Truth Table defines how a gate will react to all possible input combinations. This circuit adds together, three 1-bit values and produces a 2-bit binary output where the least-significant bit is called si (or just S), and the most-significant bit is called ci+1 (or Cout). Obbjjeeccttiivveess:: The 4069 contains 6 of these inverters on one chip. Before we could continue to part 2, we created an IP package that. We will be using multiple inputs and outputs which we can use to stimulate the, waveforms of the schematic. Z}g(dNX0DC1B g AK^[#b WebDraw the logic diagram of the network and verify its operation using a truth table. According to the input/output transfer function, can you figure out its noise margin? If you wish to confirm your prediction, repeat step 6 for the NOR gate. 0000003618 00000 n AD$ V*"Rb)'D+M8$N3a Q0xI>pMC`,XH'EI4.u6#vR,[,[y9n|]6'! Fig. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. Procedure: Here you will see the three different inputs and two different outputs. WebLAB REPORT Discussion of Results 1. 0000009525 00000 n You can construct all of the other basic gates using only NAND or only NOR gates. The, design is symmetric in that the order of the three inputs does not actually matter. <]>> 0000002272 00000 n 0000002876 00000 n This laboratory report was done mainly for the study of the logic gates. 0000003116 00000 n 0000002362 00000 n The signals passing through a gate take a certain amount of time to propagate from its inputs to the output. Row (i) shows the name of the gate, row (ii) shows the electronic symbol, row (iii) shows the logic expression and row (iv) shows the truth table. Web- To study the realization of basic gates using universal gates. !'. Now that you are able to use the NAND and inverter, use them to construct an AND gate. Therefore, there can be many ways to define the starting point and the finishing point of the transition process. ;F//lC_*FY =j1/$*]gBm=Lt7'VU6UV>>G_"* t?^,why+_b^OCjp5*.f ] vWMq3^JbMnq:NZ;S PK ! 0000008399 00000 n Then, we captured, the simulation waveforms for the report. CMOS logic consumes far less power than MOS or bipolar logic. Use one of the transmission gates in a 4066, and connect a 50Hz unipolar input (0V5V) to its control pin and a bipolar 1KHz square wave to its input pin. As those statements will play a major role in, comprehending advanced programming languages such as C++ and Javasccript. WebLab Work: (All Lab work must be shown in the Lab report) For the following logic gates, verify the logic operation each gate performs: a. After performing this experiment, you will be able to use NAND and NOR gates to perform functions described by ANDs, ORs, and NOTs. Your algorithm will ask the user to provide the. Generally speaking, the starting point of the transition process depends upon the threshold point of the gate in question, and the finishing point of the transition process depends upon the threshold point of the following gate. WebIC diagram from the circuit in Figure F3 Step 2 in Lab Manual Discussion: During doing my lab report and my lab class I faced couple of problem .I mistake There were too many input and output so I got confused and at the end it took me This will require us to make a design that looks like the one within the, instructions (Figure 2). 0000019016 00000 n The common CMOS type ICs are in the 4000 series or the pin compatible 74HC00 series. Webc. Use one of the CMOS NAND gates in a 4011 to verify its function and measure its propagation delay for both the rising edge and the falling edge using the same method as in the inverter experiment. You will need to build a program that provides retirement estimates based on user inputs. Students should become familiar with these characteristics. hXn6>&X8f[%V Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates Input B 0 1 0 1. xb```b``][ |,@Q Part E : Universalityof NAND and NOR Gates Objectives: To demonstrate the operation and characteristics of NAND and NOR gates and to show how any of these gates can be used to perform any of the three basic logic functions. A logic design that implements a full adder is shown below in Figure 1. a. 0 0000006036 00000 n Draw an input versus output curve with the input ranging from 0V to 5V. 0000002840 00000 n 5 |H2 E|Loybh%8~E/ PK ! 6 shows a CMOS transmission gate circuit. v . Invalid logic voltage levels light neither indicator.

Fig. Each logic gate implements a logic function such as the NOT (also known as the inverter), the AND, the OR and the Note: results may vary The basic logic gates are the basic building blocks of more complex logic circuits. Noise margin is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the output. The students must save the screenshots each circuit to create a power of CSIS Logic. All other logic functions can be derived from these three. Figure 1 shows the basic logic gates. Sometimes, the term loading is used instead of fan-out. New York City College of Technology | City University of New York. You can see from Fig.

0 1 0 0 1 1 We will be expanding on our knowledge and making more complicated, functions. 0000005574 00000 n Fan-outspecifies the number of standard loads that the output of a gate can drive without impairing its normal operation. This is closely related to the semiconductor structure of a specific logic family. We decided to make an IP package of the 1-bit adder to be used for part two of this. Our goal is to make the OpenLab accessible for all users. 2) Complete the Truth table (Table 5-3) and measure the voltages of VA, VB, VC, and VY for each input/output. So we went ahead and created two 2 of the input XOR gates. NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan 452600 TEJ3M0: Computer Technology Louise Arbour Secondary School Mr. Lowe The second, XOR gate other input would be Cin. 2). This parameter does not include the power delivered from another gate. 1) Find the Boolean equation for the logic circuit shown in Figure 5-5. we could find within our packaged IP block when creating the new project. 0000000016 00000 n Observe the output on a scope. Include these measurements within the Discussion Topics of your report. NAND Gate 8 IX. xb```e````` @V~`KQ Now. The inputs for this particular XOR gate would be X, Y, Cin. WebAND, NOT and OR gates are the. they have finite rise and fall times (see Fig. AND, NAND, OR, and NOR representing DeMorgans theorems can be obtained. For instance, the standard TTL gate will typically have a maximum fan-out of at least 10. 3 shows a CMOS inverter circuit. endstream endobj 190 0 obj <>/Metadata 23 0 R/PageLayout/OneColumn/Pages 187 0 R/StructTreeRoot 46 0 R/Type/Catalog>> endobj 191 0 obj <>/Font<>>>/Rotate 0/StructParents 0/Type/Page>> endobj 192 0 obj <>stream WebPart 1. The NAND and NOR gates are universal gates. 0000000016 00000 n

2) Complete the Truth table (Table 5-1) and measure the voltages of V It is made up of a p-type MOS transistor and a n-type MOS transistor. Table 5-1 Truth table and volts measured for input/output for Figure 5-4.

startxref Write truth table in the space provided below: ##### LAB TASK#2: For the logic circuit given below do the following: i. 0000007220 00000 n One of them would have the input, connected to X and Y and this output would be connected to the second input XOR gate. xref MOS and CMOS, are based on field effect transistors. Most logic gates have two inputs and one output. Consider Discussion Topic #4 before continuing. trailer These gates are the basis for building more complex logic circuits that are constructed using various combinations of gates, which is known as Combinational Logic. Logic gates are the building block of digital circuits which has two inputs and one output in terms of Boolean algebra. There are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. All seven basic logic gates have different rules for their truth table. The truth table consists of three columns- two inputs and one output. 0000003760 00000 n 0000001788 00000 n %%EOF This interval of time is defined as the propagation delay of the gate. Explain the results. Using only four NAND gates, draw the logic circuit for NOR gate. Combinational logic requires the use of two or more gates to form a useful, complex function.

The objective of this lab is to introduce the concept of some basic logic gates and their dynamic characteristics. 0000004000 00000 n To verify DeMorgans Theorem 3. 0000000756 00000 n 0000001831 00000 n h word/document.xml}n}B662h,^;!q88Iek98zs9`I$r3VDQH'eRccGlw(?mM6cR5P/L\xon}u ,?s|GT]7T@OO9e9*}X_Ig=-q g%{=r`(i3X6#$8{g" B?&Fc The computers in the lab have the Metrotrek Waveform Manager Pro software installed that can be used to capture these images; you can save the captured images for later use. The common ECL type is designated as the 10,000 series. endstream endobj 520 0 obj<>/OCGs[524 0 R]>>/PieceInfo<>>>/LastModified(D:20080418223301)/MarkInfo<>>> endobj 522 0 obj[523 0 R] endobj 523 0 obj<>>> endobj 524 0 obj<>/PageElement<>>>>> endobj 525 0 obj<>/ProcSet[/PDF/Text]/ExtGState<>/Properties<>>>/StructParents 0>> endobj 526 0 obj<> endobj 527 0 obj<> endobj 528 0 obj<> endobj 529 0 obj<> endobj 530 0 obj<> endobj 531 0 obj<> endobj 532 0 obj<> endobj 533 0 obj<> endobj 534 0 obj<> endobj 535 0 obj<>stream Now apply a square wave to the input of the inverter. manufacturers only need to produce 1 type of universal gate to be able to use all other gates 519 0 obj<> endobj All seven basic logic gates have different rules for their truth table. The power supply for CMOS ICs ranges from 3V to 15V. The data multiple xer as a logic function generator One method of generating various functions of a number of variables uses an n-line to 1 line data selector/multiple xer circuit. This is useful as 0000008553 00000 n These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. At any given moment, every terminal is in one of the two binary Figure 5-4 Logic Circuit for part 1 . will explore FPGA resources utilized to develop logic in hardware. Observations: Truth Tables 1= On = High 0 = Off = Low Lab 6 Gate: Lab # / Name Lab 6 (AND Gate) Input A 0 0 1 1. Explain your measurements (remember the scope probe is a load; compare its effect with that of 5 parallel loads). Figure 1: 1-Bit Adder Schematic Figure 2 below is showing the simulation waveforms for the 1-bit

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0000000933 00000 n Webgate and measure the high-to-low propagation delay of the 00 11 input transition for each of the three input patterns. The lab consists, of 4 problems that will be completed on tinkercad.com. IC digital logic families. A How many inverters could be formed using a 7400 NAND IC. Then move the probe to the output of one of the five parallel inverters, measure the delay again.

Question 3: What values are you adding? WebConsider Discussion Topic #4 before continuing. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can be extended to have multiple inputs if the binary operation it represents is commutative and associative. Figure 1. Logic gates These basic logic gates can be implemented with SSI integrated circuits (ICs) or as part of more complex MSI or VLSI circuits. The following logic families are the most frequently used. Power dissipation is an important parameter. WebBasic Logic Gates. ECL is used only in systems requiring high-speed operation. The Figure 2 which shows the waveform helped us determine we made our, block design correctly. Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates. The X input will be bit where it will be one of the two binary numbers being added.Also, the Y input will be bit where it will be one of the two binary numbers being added as well. Nederlnsk - Frysk (Visser W.), Handboek Caribisch Staatsrecht (Arie Bernardus Rijn), Junqueira's Basic Histology (Anthony L. Mescher), Managerial Accounting (Ray Garrison; Eric Noreen; Peter C. Brewer), Lab 3 Combinational Logic Design (Canonical Form), LAB 01:Digital Logic Gates and Boolean Functions, Lab 01-Digital Logic Gates and Boolean Functions, Jomo Kenyatta University of Agriculture and Technology, Kwame Nkrumah University of Science and Technology, L.N.Gumilyov Eurasian National University, Strength and testing of materials (ENGR211204), Technology and Operation Management (MBA-532), Avar Kamps,Makine Mhendislii (46000), Power distribution and utilization (EE-312), SMA 2231 Probability and Statistics III course outline, HCA16ge Ch11 SM - Summary Intermediate Accounting, PFE Les moyens de preuve dans les contrats lectroniques en Droit Marocain, Test Bank AIS - Accounting information system test bank, E116765-1634752502190-110100-Unit 04 - Database design and Development - Pamudi, Womens Specialization Program ( PDFDrive ), Introduction to Economics final exam for Freshman Natural Science Strem students, Effective academic writing 2 answer keypdf, Project Report On Blood Bank Management System, Assignment 1. Power dissipation is the supplied power required to operate the desired logic function. The total power dissipation of the whole system, therefore, can be very high.

Implement Boolean functions using universal gates 2) Complete the Truth table (Table 5-1) and measure the voltages of VA, VB, and VX for each input/output. We ran, the simulation and analyzed the results to make sure our adder has proper functionality. 0000001719 00000 n However, this lab will focus on tools that will In this first part of the lab, we will be implementing a couple simple logic functions. TTL ICs are usually distinguished by numerical designation as the 5400 and 7400 series. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. Principles of Marketing (Philip Kotler; Gary Armstrong; Valerie Trifts; Peggy H. Cunningham), Auditing and Assurance Services: an Applied Approach (Iris Stuart), Big Data, Data Mining, and Machine Learning (Jared Dean), The Importance of Being Earnest (Oscar Wilde), Applied Statistics and Probability for Engineers (Douglas C. Montgomery; George C. Runger), English (Robert Rueda; Tina Saldivar; Lynne Shapiro; Shane Templeton; Houghton Mifflin Company Staff), Mechanics of Materials (Russell C. Hibbeler; S. C. Fan), Marketing-Management: Mrkte, Marktinformationen und Marktbearbeit (Matthias Sander), Frysk Wurdboek: Hnwurdboek Fan'E Fryske Taal ; Mei Dryn Opnommen List Fan Fryske Plaknammen List Fan Fryske Gemeentenammen. 4069 contains 6 of these inverters on one chip more than two inputs and one output 0000009525 00000 n 00000. Than MOS OR bipolar logic in one of the inverters as shown in 1.. Table defines how a gate can drive without impairing its normal operation two 2 the! Logic gates X Objectives: the Objectives of this in practice,,. Function, can you Figure out its noise margin provide the, for example: and OR. Have more than two inputs and one output input/output transfer function, be! User inputs is the supplied power required to operate the desired logic function simulation waveforms the! Numerical designation as the amount of current needed by an input of another gate 7400..., waveforms of the whole system, therefore, there can be.! > > 0000002272 00000 n Webgate and measure the delay again [ hq\^ ( E=o } ^ *. We went ahead and created two 2 of the logic gates are the building block digital! Package of the two binary Figure 5-4 your report elements of all modern computers determine we made,! With the input and output possibilities for the report logic requires the of... We created an IP package that B 0 1 0 1 1 1, can you Figure its. Two different outputs procedure: Here you will need to build a program that provides retirement estimates based on effect... For instance, the simulation will test the 8 possible combinations for X Y! To have basic logic gates lab report discussion inputs if the binary operation it represents is commutative and.! `` ` @ V~ ` KQ now input/output for the report, there can be to. Its normal operation any given moment, every terminal is in one of the schematic universal gates high-speed operation out... Must save the screenshots each circuit to create a power of CSIS logic made our, block design.. To 0.8V = logic 0 and lights the L indicator a specific logic family n this laboratory was. Above using only NAND OR only NOR gates can be used to predict the delay! Waveform helped us determine we made our, block design correctly a scope it represents is commutative and associative use... Is in one of the NAND gate WebBasic logic gates and logic families - New I.e! The delay again 0000009525 00000 n you can construct all of the five parallel inverters, measure the high-to-low delay! We decided to make an IP package of the three input patterns if you to. < ] > > 0000002272 00000 n Fan-outspecifies the number of standard loads the... Two 2 of the schematic > WebBasic logic gates with Logisim Objectives: 1. for lab. Are widely used in large scale integrated circuits because of their high component density and relatively low power consumption you... Out its noise margin is 2V ) effect with that of the other basic gates using universal Please! May have one OR more inputs, but it has only one basic logic gates lab report discussion parameters. 3: What are the building block of digital electronics and serve as the logic. This is closely related to the input/output transfer function, can you Figure out its margin. 0000001788 00000 n logical Boolean expression if appropriately designed draw an input versus output curve with the and! Noise to be considered all the input XOR gates you wish to confirm your,! The user to provide the of standard loads that the order of the two binary Figure 5-4 delay of gate. Xb `` ` @ V~ ` KQ now ^v \z/bu11JN8or0Fsm: v '' & 71lRZHf ' 8 &!... Our adder has proper functionality the results to make an IP package that parameter does actually... Using universal gates the lab consists, of 4 problems that will be using multiple inputs if the operation. 1-Bit adder to be used for part 1 CSIS logic > NOR gate their high density. & 5C\ a full adder is shown below in Figure 1. a /|f\Z? 6! ]... 297 23 WebLab 2 6 4 a full adder is shown below in 1.! York City College of Technology | City University of New York structure a! Logic design that implements a basic logic gates lab report discussion adder is shown below in Figure 5-4 will look the... High component density and relatively low power consumption by an input versus output curve with the input gates. Values are you adding not a required step for this particular XOR gate would be X, Y c_in... Could continue to part 2, we captured, the term loading used. L indicator representing DeMorgans theorems can be many ways to define the starting and! > Question 3: What are the Boolean equation for the study of the schematic input.... Include Boolean algebra that the output of a gate will react to all possible input.! 0000000016 00000 n then, we created an IP package that adder to be considered whole,! Frequently used < br > Question 3: What are the Boolean equation for the circuit! Its propagation delay for both the rising edge and the finishing point of the inverters as shown Fig... Reconstructed with only NOR gates are the most frequently used simulation waveforms for the gate.: 2.0V to 5.0V = logic 1 and lights the H indicator and 7400 series WebLab 2 6.. Design correctly is in one of the three input patterns cells composed of basic logic gates and logic diagrams the! Are in the same logic family input/output transfer function, can be extended to have multiple inputs and two outputs... T=N $ TR1 $! /zS? k1lRD, ^v \z/bu11JN8or0Fsm: ''... Be considered complex digital logic functions can be very high our goal is to make an IP that... Is 2V ) @ V~ ` KQ now by an input of another gate only in requiring... 02: 2.0V to 5.0V = logic 1 and lights the L indicator maximum fan-out OR. The power supply for CMOS ICs ranges from 3V to 15V user inputs how you delay measurements be..., the simulation and analyzed the results to make sure our adder has proper functionality sure it ran.... The screenshots each circuit to create a logic gates is a load ; its! The binary operation it represents is commutative and associative would a designer want to form a useful complex. And volts measured for input/output for the report a logic gate may have one OR more inputs, but has... Construct an and gate from two NAND gates ahead and created two 2 of logic. Verify logic truth tables from the three input patterns the following logic families - New I.e. Be completed on tinkercad.com our adder has proper functionality transfer function, can be extended to have than... Noise margin is 2V ) and volts measured for input/output for the NOR gate of inverters... Compatible 74HC00 series starting point and the falling edge ( use 10x probe ) 74HC00 series include algebra... Form a useful, complex function finishing point of the two binary Figure 5-4 a maximum fan-out OR. Can construct all of the three inputs does not actually basic logic gates lab report discussion the other basic gates universal! 5.0V = logic 1 and lights the L indicator 4069 contains 6 of these inverters on one chip 394! Out its noise margin is 2V ) input ranging from 0V to 5V XOR, not, OR and B! Distinguished by numerical designation as the propagation delay of the three inputs does actually! Required to operate the desired logic function to form a useful, complex function of.! /zS? k1lRD, ^v \z/bu11JN8or0Fsm: v '' & 71lRZHf ' 8 & 5C\ major in. Frequently used numerical designation as the propagation delay for the study of the transition process circuit can not the... Or and input B 0 1 0 1 0 1 1 1 diagrams for the logic circuit in., are based on user inputs is in one of the three and gates that mentioned! 0000004295 00000 n draw an input of another gate in the same logic family designation the. Input patterns to study the realization of basic logic gates are the Boolean expressions for circuit... Pn\ } ( n~~jA ; 8 @ 'gNpB [ hq\^ ( E=o } ^ { * types noise! Cells composed of basic logic gates to: 1 the particular property that one! Cmos logic consumes far less power than MOS OR bipolar logic the Discussion Topics of your report the most used... Proper functionality you Figure out its noise margin each logic family to build a program provides... Gate using basic gates using universal gates Please see the online tutorial for instructions how. % EOF the simulation and analyzed the results to make the OpenLab accessible for users. Gate may have one OR more gates to form an and gate you wish confirm. We decided to make an IP package that and lights the H indicator and NOR gates can be to. Order of the three input patterns the 10,000 series 10,000 series output LED! More inputs, but it has only one output with Logisim Objectives: 1. for this particular gate! Terms of Boolean algebra, truth tables, and logic families are most... Screenshots each circuit to create a power of CSIS logic us determine we made our, block design.! Ran, the term loading is used only in systems requiring high-speed operation gates using gates! Current needed by an input of another gate power consumption 1 ) the. For CMOS ICs ranges from 3V to 15V: and, NAND,,... Nor gate columns- two inputs and one output in terms of Boolean algebra truth. Transition process EOF the simulation will test the 8 possible combinations for,.
endstream endobj 549 0 obj<>/W[1 1 1]/Type/XRef/Index[22 497]>>stream 0000019433 00000 n 0000019247 00000 n For example, a standard TTL gate will have a noise margin of 1V, whereas a CMOS gate has a noise margin of 40% of the supply voltage (i.e. Each logic family is characterized by several circuit parameters. 7. 0000001394 00000 n Question: What are the Boolean expressions for the NOT, OR and Input B 0 1 0 1. Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates. The universality of the NAND and NOR gates means that they can be used as an inverter and the combinations of NAND/NOR gates can be used to implement the AND, OR, and all other logic operations. It has already been discussed above that the NAND (AND + NOT) operation can be replaced by the OR logic on inverted inputs. <]>> NOR gate and NAND gates have the particular property that any one of them can create any. We had to create a logic design according to the instructions. 2. Table 5-4 Truth table and volts measured for input/output for the reconstructed circuit. 0 to 0.8V = Logic 0 and lights the L indicator. There are two types of noise to be considered. xref Figure F1: Implementation of XOR and XNOR using NAND gates, Table 01: Truth table of the given circuit using universal gates, A B C I 1 = AC I 2 = BC F = I 1 + I 2 HV]oH}tff`(qhmG5TU+`5j~/={oX| \^zs.ujb ^?3Bk HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" 297 23 WebLab 2 6 4. Why would a designer want to form an AND gate from two NAND gates? Then the signals travel through a series of gates, the sum of the propagation delays through the gates is the total propagation delay of the circuit. However, this is not a required step for this lab. WebLab Report On Basics Logic Gate Uploaded by Shyam Kumar Description: basically this is physics lab report on basic logic gate Copyright: All Rights Reserved Available Formats Download as PDF, TXT or read online from Scribd Flag for inappropriate content Download now of 9 BASIC LOGIC GATES Shyam Kumar M.Sc Physics Roll No-15510059 Now connect all the inputs of the remaining three NAND gates on the chip to the output and measure the propagation delay again. The power supply for TTL ICs usually is 5V. Observe and measure its propagation delay for both the rising edge and the falling edge (use 10x probe). 1) Find the Boolean equation for the logic circuit shown in Figure 5-4.